Non-volatile solid-state read/write memory devices are now commonplace in many electronic systems, particularly in portable electronic devices and systems. A common technology for realizing non-volatile solid-state memory devices, more specifically for realizing electrically erasable programmable memory devices, utilizes “floating-gate” transistors to store the data state. According to this conventional technology, the memory cell transistor is “programmed” by biasing it so that electrons tunnel through a thin dielectric film onto an electrically isolated transistor gate element. The trapped electrons on the floating gate will raise the apparent threshold voltage of the memory cell transistor (for n-channel devices), as compared with the threshold voltage with no electrons trapped on the floating gate. This difference is made apparent by different source-drain conduction under normal transistor bias conditions. Modern non-volatile memory devices are “erasable” in that the memory cell transistors can be biased to remove the electrons from the floating gate, again by way of a tunneling mechanism. “Flash” memory devices are typically realized by such non-volatile memory arrays, in which the erase operation is applied simultaneously to a large number (a “block”) of memory cells.
According to one approach, non-volatile memory cells are realized by metal-oxide semiconductor (MOS) transistors having two polysilicon gate electrodes. A control gate electrode is electrically connected to provide an electrical connection with other circuitry in the integrated circuit, and a floating gate is disposed between the control gate electrode and the channel region of the memory transistor. In this conventional construction, electrons tunnel to the floating gate upon application of a high programming voltage to the control gate (which capacitively couples to the floating gate) relative to the source and drain regions of the memory transistor.
Because of the convenience and efficiency of modern flash memories, it is now desirable and commonplace to embed flash memory within larger scale integrated circuits, such as modern complex microprocessors, digital signal processors, and other large-scale logical circuitry. Such embedded memory can be used as non-volatile program memory storing software routines executable by the processor, and also as non-volatile data storage. On a smaller scale, flash memory cells can be used to realize control registers from which a larger scale logical circuit can be configured, and also to “trim” analog levels after electrical measurement.
State of the art processes used to integrate flash memory into larger scale integrated circuits typically employ an additional gate oxide layer and a dual-level polysilicon architecture to obtain non-volatile memory cells. This dual-level polysilicon architecture adds significant complexity to the design of the integrated circuit, in addition to the process steps required to fabricate the dual-level architecture. For many applications, such as small-batch integrated circuit manufacturing operations, it is not time or cost effective to employ a dual-level architecture.
Accordingly, it is desirable to provide integrated circuits and methods for fabricating integrated circuits with improved non-volatile memory devices. In addition, it is desirable to provide integrated circuits and methods for fabricating integrated circuits that do not require a dual-level polysilicon architecture. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.